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| PHB95N03LTA TrenchMOSTM logic level FET Rev. 01 -- 27 August 2002 M3D166 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOSTM technology. Product availability: PHB95N03LTA in SOT404 (D2-PAK). 2. Features s Low on-state resistance s Fast switching. 3. Applications s High frequency computer motherboard DC to DC converters. 4. Pinning information Table 1: Pin 1 2 3 mb Pinning - SOT404 simplified outline and symbol Description gate (g) mb Simplified outline Symbol drain (d) source (s) mounting base, connected to drain (d) [1] d g 2 1 3 MBK116 MBB076 s SOT404 (D2-PAK) [1] It is not possible to make connection to pin 2 of the SOT404 package. Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 Tj 175 C Tmb = 25 C; VGS = 5 V Tmb = 25 C VGS = 10 V; ID = 25 A; Tj = 25 C VGS = 5 V; ID = 25 A; Tj = 25 C Typ 4.8 7.5 Max 25 75 125 175 6 9 Unit V A W C m m drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR ID VGS IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) drain current (DC) gate-source voltage peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 C peak source (diode forward) current Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 75 A; tAL = 0.1 ms; VDD = 15 V; RGS = 50 ; VGS = 5V; starting Tj = 25 C; unclamped inductive load; VDD = 15 V; RGS = 50 ; VGS = 5V; starting Tj = 25 C Tmb = 25 C; pulsed; tp 10 s; Figure 3 Tmb = 25 C; Figure 1 Conditions 25 Tj 175 C 25 Tj 175 C; RGS = 20 k Tmb = 25 C; VGS = 5 V; Figure 2 and 3 Tmb = 100 C; VGS = 5 V; Figure 2 Min -55 -55 Max 25 25 75 61 20 240 125 +175 +175 75 240 120 Unit V V A A V A W C C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy IDS(AL)S non-repetitive drain-source avalanche current - 75 A 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 2 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 120 Pder (%) 80 03aa16 120 Ider (%) 80 03ad94 40 40 0 0 50 100 150 200 Tmb (C) 0 0 50 100 150 200 Tmb (C) P tot P der = ---------------------- x 100% P tot ( 25 C ) ID I der = ------------------ x 100% I D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 103 03ad77 ID (A) Limit RDSon = VDS / ID tp = 10 s 100 s 102 1 ms DC 10 10 ms 100 ms 1 1 10 VDS (V) 102 Tmb = 25 C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 3 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 7. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions minimum footprint; mounted on a PCB Min Typ Max Unit 50 1.2 K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient Symbol Parameter 7.1 Transient thermal impedance 10 Zth(j-mb) (K/W) 1 = 0.5 0.2 10-1 0.1 0.05 0.02 P 03ad76 = tp T 10-2 single pulse tp T t 10-3 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 4 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain-source leakage current VDS = 25 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 5 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 C Tj = 175 C VGS = 10 V; ID = 25 A; Tj = 25 C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 IS = 40 A; VGS = 0 V VDD = 15 V; ID = 15 A; VGS = 10 V; RG = 6 ; resistive load VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 50 A; VDD = 12 V; VGS = 4.5 V; Figure 13 43 12 16 770 500 10 30 110 80 0.85 0.9 20 50 140 100 1.2 nC nC nC pF pF pF ns ns ns ns V V 4.8 6 m 7.5 13 9 15.5 m m 0.05 10 10 500 100 A A nA 1 0.5 1.5 2 2.3 V V V 25 22 V V Conditions Min Typ Max Unit 2200 - Source-drain diode 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 5 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 80 ID (A) 60 10 V 5 V 3.5 V 03ad78 80 ID (A) 60 VDS > ID x RDSon 03ad80 Tj = 25 C 40 3V 40 20 VGS = 2.5 V 0 0 0.5 1 1.5 VDS (V) 2 20 175 C Tj = 25 C 0 0 1 2 3 VGS (V) 4 Tj = 25 C Tj = 25 C and 175 C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 0.05 RDSon () 0.04 2.5 V VGS = 3 V 03ad79 2 a 1.5 03ad57 Tj = 25 C 0.03 1 0.02 3.5 V 0.5 0.01 5V 10 V 0 0 20 40 60 ID (A) 80 0 -60 0 60 120 Tj (C) 180 Tj = 25 C R DSon a = --------------------------R DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 6 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 0 60 120 Tj (C) 180 10-6 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 104 03ad83 C (pF) Ciss 103 Coss Crss 102 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 7 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 80 IS (A) 60 VGS = 0 V 03ad82 10 VGS (V) 8 Tj = 25 C ID = 50 A VDD = 6 V 6 03ad84 12 V 24 V 40 4 20 175 C Tj = 25 C 2 0 0 0.3 0.6 0.9 1.2 VSD (V) 0 0 30 60 QG (nC) 90 Tj = 25 C and 175 C; VGS = 0 V ID = 50 A; VDD = 6 V, 12 V and 24 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 8 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 9. Package outline Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 Fig 14. SOT404 (D2-PAK) 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 9 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 10. Revision history Table 6: 01 Revision history CPCN Description Product specification; initial version Rev Date 20020827 9397 750 10027 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 10 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET 11. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 13. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 14. Trademarks TrenchMOS - is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 10027 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 27 August 2002 11 of 12 Philips Semiconductors PHB95N03LTA TrenchMOSTM logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 27 August 2002 Document order number: 9397 750 10027 |
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